The present invention relates to data communications and more specifically to a structure and method for redundancy replacement in high-speed data communications circuitry.
Different types of systems are available today for providing high-speed data communications. Some systems require all communications to be transmitted using the same communication protocol layer stack. Other systems require communications to be transmitted at a particular transmission rate. The Unilink family of serializer-deserializer (SerDes) integrated circuits (“ICs” or “chips”)cores offered by the assignee of the present invention, provides flexible choice over the communication protocol layer stack and the transmission rate.
Such SerDes cores chips have multiple adapters cores including data transmitters and receivers for integration into application specific integrated circuits (“ASICs” or “chips”). Chips containing SerDes cores typically include one or more additional functional elements, such as a processor. Each SerDes cores core supports multiple serial data links per chip as either unidirectionally (transmitting or receiving only) or bidirectionally (transmitting and receiving) configured chips. Unilink SerDes cores provide flexible design elements as they are integratable with other circuit block and functional element block libraries offered by the assignee of the present invention in complementary metal oxide semiconductor (CMOS) technology.
SerDes cores are intended primarily for providing chip-to-chip, and card-to-card interconnection, having transmitter and/or receiver units that operate at signal switching speeds above about 500 MHz, at data rates from above about 500 megabits per second (Mbs) up to many gigabits per second (Gbs). At such speeds, SerDes cores are utilized to replace a moderate rate parallel data bus with a single high-speed link. This significantly reduces the number of input output connections to and from the chip, simplifies system integration, and reduces overall system cost. In addition, SerDes cores are frequently used in groups of multiple links to achieve wider data paths, and consequently even higher data throughput.
The need for chips having high-speed SerDes cores increases as the demand for increased communication bandwidth and data processing speeds increases. FIG. 1 is a prior art diagram illustrating an environment 100 in which chips having SerDes cores are typically used. As shown in FIG. 1, a first SerDes core 150 is integrated into a chip mounted to a first card 110. The SerDes core 150 is shown having first and second transmitter blocks 130A and 130C, each having four transmitters, and first and second receiver blocks 130B and 130D, each having four receivers. Typically, SerDes cores include a large number of transmitters and receivers, for example, 128 pairs to 512 pairs of transmitters and receivers being available in one such core design. The SerDes core 150 forms a portion of a first chip which is mounted to a card 110 connected to a backplane 190 via a connector 170. At another position of the backplane 190, a second card 120 is connected via connector 171, the card 120 also having a SerDes core 160 integrated on a chip mounted thereto. Like SerDes core 150, the SerDes core 160 is shown having first and second transmitter blocks 140B and 140D and first and second receiver blocks 140A and 140C. In such arrangement, a transmitter of the transmitter block 130A of the SerDes core 150 transmits data in a first direction over a cable 182 of the backplane 190 to a receiver of the receiver block 140A of the SerDes core 160. A transmitter of transmitter block 140B of SerDes core 160 transmits data in a second direction (return direction) over another cable 180 to a receiver of receiver block 130B of SerDes core 150.
As mentioned above, in the environment 100 (FIG. 1) 128 pairs of high-speed data receivers and data transmitters are provided in each SerDes core of a custom chip. Given the operational performance required from each transmitter and receiver, and the number of receivers and transmitters provided in each chip having a SerDes core, it is likely that one or more receivers and transmitters on a chip will fail at some time, either during post-production testing or later when installed for use. As the number of receivers and transmitters per chip is increased, the likelihood that a receiver or a transmitter will fail increases further. At present, the response to such failure is to declare the entire chip unusable and to scrap the chip, even though the failing transmitter or receiver is only a small part of the chip, and many other transmitters and receivers remain in working order. One need of the SerDes core design is to provide a structure and method for replacing transmitter or receiver elements with an available redundancy transmitter or a redundancy receiver.
A redundancy replacement arrangement used in a memory array according to the prior art is illustrated in FIG. 2. As shown in FIG. 2, input signal lines di1 through di4 are coupled by a set of multiplexers 10, 20, 30, and 40 to output signal lines do1 through do4. A redundancy input line rdi is also coupled to each of the multiplexers 10 the redundancy input line rdi being coupled to a redundancy data transmitter or redundancy data receiver. Each multplexer is implemented by an inverter, a pair of transmission gates and a pair of redundancy transmission gates, all implemented by complementary metal oxide semiconductor field effect transistors (CMOSFETs). For example, multiplexer 20 is implemented by an inverter (INV2), a pair of transmission gates T21, and a pair of redundancy transmission gates T22. When upstream devices (not shown) that are connected to the input signal lines di1-di4 are operational, the control inputs c1 through c4, being at normally inactive states, select the input signal lines for connection to the output signal lines do1 through do4. However, when an upstream device is not operational, one of the control inputs is activated, such that the multiplexer to which it is attached selects the redundancy input signal line rdi instead. For example, when control signal c2 is active (at a high voltage state), the multiplexer 20 selects the redundancy input line rdi for output to the output signal line do2 in place of the input signal line di2.
While the prior art arrangement shown in FIG. 2 performs acceptably within a memory array, two problems of the prior art arrangement of FIG. 2 make it unsuitable for use in high-speed SerDes cores operating at signal switching speeds above about 500 MHz. First, the MOSFETs used as transmission gates of the default signal path, for example gates T21 of multiplexer 20, introduce jitter noise which restrains the bandwidth of the signals passed from input signal lines dil-di4 to dol-do4. Second, the redundancy signal path from redundancy signal line rdi to output signal line suffers from high parasitic junction capacitance. The redundancy signal line rdi is connected to all redundancy transmission gates, i.e. gates T12, T22, T32 and T42, such that all of the MOSFETs of the transmission gates contribute to the parasitic junction capacitance. Such parasitic junction capacitance reduces the transmission bandwidth of signals on the redundancy signal input line rdi even more so than the jitter noise caused by the transmission gates of the default signal path. Both of these problems make redundancy replacement arrangements using MOSFET transmission gates unsuitable for signal switching speeds above about 500 MHz.
Therefore, it would be desirable to provide a redundancy replacement arrangement for a high-speed communications circuitry adapter. It would further be desirable to provide a redundancy replacement arrangement suitable for high speed communications circuitry operating above about 500 MHz.
It would further be desirable to provide a redundancy replacement arrangement having increased bandwidth relative to those in which MOSFET transmission gates are utilized.